A Novel Logic Locking Technique with Observability Measures to Thwart Hardware Trojans

Abstract

Hardware attacks like the overproduction of integrated circuits, intellectual property piracy, reverse engineering, and hardware trojans are major threats for long years. To safeguard critical circuits from these threats, encrypting the circuit from attackers is the only way. In this paper, among the testability measures, the observability values are considered a key parameter for performing the logic locking. Detecting the nets with low observability values and improving the values make those net signal values harder to observe by the attacker and in addition obfuscates the circuit. The experiment is performed on ISCAS’85 benchmark circuits and it is ensured the circuits are locked with a secret key. The testability measurement tool is used to extract the observability measures of the benchmark circuits.