Parallel multiplier designs utilizing a non-binary logic scheme

Abstract

The paper presents a novel approach for CMOS low-power, high performance parallel multiplier design, utilizing a recently proposed non-binary shift switch logic scheme. Compared with the existing well-known parallel multiplier designs, the new approach requires fewer partial product bit reduction stages, and improves performance in speed, VLSI area as well as power dissipation. SPICE simulations with a 0.25 micron, 2.5 volt supply process on critical paths have demonstrated the superiority of the approach.