Design of Low Power Digital Phase Lock Loops

Abstract

Until recently, a vast majority of PLLs have been Analog PLLs (APLLs). The block schematic of a commonly used APLL is shown in Fig. 1. Here, divided versions of an input reference clock and the output of a Voltage Controlled Oscillator (VCO) are compared in Phase Frequency Detector (PFD), which in conjunction with a Charge Pump and a low pass loop filter generates a control signal for the VCO. This results in a phase lock between REFINT and FBCLK, making fo,t equal to M/NQ times fREF. Thus, the output frequency can be programmed by means of M, N and Q.