A Novel Structure of Cascaded Multilevel Inverter with High Voltage Level Generation Capability using Reduced Components

Rojalin Rout, T. Roy, T. R. Choudhury, B. Nayak
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Abstract

A novel cascaded multilevel inverter structure is presented in this paper. The presented topology possesses the capability to generate large number of voltage levels at output terminals using significantly lower number of components. The basic unit of proposed topology is asymmetric in nature and can produce 35 levels using 6 unidirectional switches and 4 bidirectional switches and 6 input dc sources of magnitude V/2, V/2, V, V, 3V, 3V. Further, cascaded MLI structure has been developed by using the proposed basic unit. The cascaded structure can produce better quality of output voltage using minimum components. The proposed topology has been compared with the relevant recently developed topologies with respect to different perspective such as required switching devices, isolated dc sources, gate driver circuit for generating specific voltage level. Further, the stress voltages across the switches have been evaluated and compared with the other topologies. It is observed that the topology requires minimum components and provides minimum Total standing voltage for generating specific output level with respect to other topologies. The effectiveness of proposed topology is verified by an extensive simulation study of 35 level MLI structure with different load condition such as RL, L, and sudden load change condition.
一种采用简化元件的高电压级联多电平逆变器结构
提出了一种新型的级联多电平逆变器结构。所提出的拓扑结构具有在输出端使用较少数量的元件产生大量电压电平的能力。所提出的拓扑的基本单元本质上是不对称的,使用6个单向开关和4个双向开关和6个输入dc源,大小为V/2、V/2、V、V、3V、3V,可以产生35个电平。此外,利用所提出的基本单元,还开发了级联MLI结构。级联结构可以用最少的元件产生更好的输出电压质量。从不同的角度,如所需的开关器件、隔离直流电源、产生特定电压水平的栅极驱动电路等,将所提出的拓扑结构与最近开发的相关拓扑结构进行了比较。此外,还评估了开关上的应力电压,并与其他拓扑结构进行了比较。可以观察到,相对于其他拓扑结构,该拓扑结构需要最小的组件,并提供最小的总驻电压以产生特定的输出电平。通过对35级MLI结构不同载荷条件(RL、L、载荷突变条件)的仿真研究,验证了所提拓扑的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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