Design of fault-tolerant cellular arrays on multiple-valued logic

N. Kamiura, Y. Hata, K. Yamato
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引用次数: 4

Abstract

This paper discusses the problems of the design and the fault tolerance in multiple-valued cellular arrays by considering the single-level array, the two-level array and the three-level array. These arrays are constructed by some cells that have the unique switch operation. It assumes the stuck-at-0 fault and the stuck-at-(k-1) fault of the switch cells on k-valued cellular arrays. The fault-tolerant arrays for the single fault are constructed by building a duplicate row and a duplicate column iteratively in the arrays. By evaluating three types for the design, the fault tolerance and the testability for multiple faults, it clarifies that the two-level array is the most suitable structure. Finally, the comparison with formerly presented arrays shows advantages for our fault-tolerant two-level array.<>
基于多值逻辑的容错元胞阵列设计
本文从单级阵列、两级阵列和三级阵列三方面讨论了多值蜂窝阵列的设计和容错问题。这些数组是由一些具有独特开关操作的单元格构成的。假设k值元胞阵列上的开关单元存在卡在0故障和卡在(k-1)故障。通过在数组中迭代地构建重复行和重复列来构建单故障容错数组。通过对三种类型的设计、容错性和多故障可测试性的评价,明确了两级阵列是最合适的结构。最后,与以前提出的数组的比较显示了我们的容错两级数组的优点
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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