High-speed comparator architectures for fast binary comparison

Abstract

This paper proposes the design of digital comparator with two different parallel architectures. These comparators are first realized in Verilog and simulated with Xilinx ISE 8.2i platform and then compared with the traditional design. Simulation results show that the first proposed architecture has 23.769 % less combinational delay (logic + interconnect) and the second proposed architecture is even much faster and has a combinational delay of 35.218 % less compared to the traditional design.