Digital Assisted Current Sensing Scheme for on-chip Power Management

Abstract

In this paper, we introduce a current sensing scheme for on-chip power management. The proposed scheme uses the voltage drop across the MOSFET switch in a DC-DC converter for sensing the current and a time-domain circuitry for digitization. Minimal use of analog circuitry in the architecture not only reduces the power consumption but also makes the design simple to realize. The scheme offers tolerance against variations in process and temperature by comparing the sensed voltage against a reference voltage that is reflective of the amount of variation present. Proposed circuit schematic was designed and simulated using 55nm CMOS technology alongside a switching regulator. The simulated circuit could measure currents up to 600mA with a maximum measurement error of only +/−2.5%. The proposed scheme could measure current within a measurement time of 2uS while consuming only 200uA from a 1.8V supply.