FPGA-Based Evaluation and Implementation of an Automotive RADAR Signal Processing System using High-Level Synthesis

Abstract

HLS enables the design of optimized hardware from behavioral specifications using HLL such as C, C++, and SystemC. Hardware designs were traditionally developed using HDLs such as Verilog, VHDL etc. at the Register Transfer Level. Recently HLS has been gaining popularity due to increasingly better QoR, high productivity and lower development times. HLS gives software developers the ability to implement their designs on FPGAs without requiring detailed knowledge of RTL technologies and HDL. A high-level model for HLS of an automotive RADAR signal processing system has been investigated for the purpose of comparison between hardware design using HLS model and an existing HDL model. A synthesized design of an automotive RADAR signal processing system using Xilinx Vivado HLS-based design methodology is presented in this paper which can be depicted as a mid to high complexity, real world application. Various HLS techniques have been used to optimize the design for both speed and resource utilization while providing a much shorter development time. The FPGA resource utilization increased but it was well under 5% of the total resources available on the FPGA chip, achieving a speed up of 2x when compared to the RTL-based design for the RADAR system while at the same time reducing the development time by 60%.