Chip-scale physical interconnect models (Tutorial)

Abstract

Modeling layout-dependent interconnect processing steps is useful to predict integrated circuit design behavior. We illustrate key data and steps in developing etch, electrochemical deposition (ECD), and chemical-mechanical polishing (CMP) models in order to predict chip topography. We utilize an interferometer for validation of models for the first time. Such models are useful to select optimal fill algorithms using a novel DOE-based flow as proposed herein.