Improving binary compatibility in VLIW machines through compiler assisted dynamic rescheduling

Abstract

One of the main problems that prevents extensive use of VLIW architectures for non-numeric programs is lack of object code (or binary) compatibility among different implementations of the same architecture. This is due to exposing all architectural features to generate code at compile time. New features of a VLIW machine may lead to incorrect results by executing the code compiled for the older machine. In this paper, a new approach to overcome this problem is presented, which we call dynamic VLIW generation (DVG). It is performed with the help of code annotation provided by the compiler, to reduce the complexity of the required hardware. In the DVG technique, operations are rescheduled for the new machine at the time of instruction cache miss repair. In this way, the rescheduler hardware is not located in the execution pipeline engine avoiding potentially longer cycle times. To simplify the dependency checking hardware, dependency information is encoded for each operation at compile time. This information can be combined into the final binary code, or may be provided as a separate file, which can be loaded into memory at execution time by the OS loader. In this technique operations can be rescheduled speculatively and a mechanism is presented to prevent destroying the contents of live registers. Experimental results show that the performance of rescheduled code using the DVG technique is about 10% worse than code compiled directly for the target processor.