A methodology for power characterization of associative memories

Dawei Li, S. Joshi, S. Memik, J. Hoff, S. Jindariani, Tiehui Liu, J. Olsen, N. Tran
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引用次数: 4

Abstract

Content Addressable Memories (CAM) have become increasingly more important in applications requiring high speed memory search due to their inherent massively parallel processing architecture. We present a complete power analysis methodology for CAM systems to aid the exploration of their power-performance trade-offs in future systems. Our proposed methodology uses detailed transistor level circuit simulation of power behavior and a handful of input data types to simulate full chip power consumption. Furthermore, we applied our power analysis methodology on a custom designed associative memory test chip. This chip was developed by Fermilab for the purpose of developing high performance real-time pattern recognition on high volume data produced by a future large-scale scientific experiment. We applied our methodology to configure a power model for this test chip. Our model is capable of predicting the total average power within 4% of actual power measurements. Our power analysis methodology can be generalized and applied to other CAM-like memory systems and accurately characterize their power behavior.
联想记忆的功率表征方法
内容可寻址存储器(CAM)由于其固有的大规模并行处理架构,在需要高速内存搜索的应用中变得越来越重要。我们提出了CAM系统的完整功率分析方法,以帮助探索其在未来系统中的功率性能权衡。我们提出的方法使用详细的晶体管级电路模拟功率行为和少量输入数据类型来模拟全芯片功耗。此外,我们将我们的功率分析方法应用于定制设计的联想记忆测试芯片。该芯片是由费米实验室开发的,目的是在未来大规模科学实验产生的大容量数据上开发高性能实时模式识别。我们应用我们的方法来为这个测试芯片配置一个功率模型。我们的模型能够在实际功率测量值的4%以内预测总平均功率。我们的功率分析方法可以推广并应用于其他类cam存储系统,并准确表征其功率行为。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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