Mengdi Cao, Luqiang Duan, Guopei Chen, Ruichang Ma, Zhiyuan Chen, B. Chi
{"title":"A Ka-Band Low Noise Amplifier for Phased Array Radar System in 65nm CMOS","authors":"Mengdi Cao, Luqiang Duan, Guopei Chen, Ruichang Ma, Zhiyuan Chen, B. Chi","doi":"10.1109/EDSSC.2019.8754111","DOIUrl":null,"url":null,"abstract":"An optimized Ka-band low noise amplifier (LNA) for phased array radar system is presented in this paper. Two gain-boosting techniques are quantitatively analyzed and employed on the proposed LNA to achieve high gain and low noise performances. Meanwhile, three switched-capacitor arrays are inserted to prevent the center frequency (35GHz) from shifting with the PVT variations. Implemented in 65nm CMOS, the presented LNA features 26.2dB gain over 7GHz-3dB bandwidth (BW-3dB) while drawing 24.5mA current from one 1V power supply. The noise figure (NF) is lower than 3.4dB at 35GHz. S11 and S22 are below -10dB within the entire operating frequency band (33GHz-37GHz). The input third-order intercept point (IIP3) is higher than -22dBm.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"7 6","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2019.8754111","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
An optimized Ka-band low noise amplifier (LNA) for phased array radar system is presented in this paper. Two gain-boosting techniques are quantitatively analyzed and employed on the proposed LNA to achieve high gain and low noise performances. Meanwhile, three switched-capacitor arrays are inserted to prevent the center frequency (35GHz) from shifting with the PVT variations. Implemented in 65nm CMOS, the presented LNA features 26.2dB gain over 7GHz-3dB bandwidth (BW-3dB) while drawing 24.5mA current from one 1V power supply. The noise figure (NF) is lower than 3.4dB at 35GHz. S11 and S22 are below -10dB within the entire operating frequency band (33GHz-37GHz). The input third-order intercept point (IIP3) is higher than -22dBm.