A cycle-level parallel simulation technique exploiting both space and time parallelism

Abstract

As the number of processors increases in an MPSoC, the simulation performance degrades significantly if all component simulators run sequentially. Recently a novel parallel simulation technique was proposed to exploit space-parallelism by distributing component simulators to multiple host cores. In this paper, we boost the performance further by exploiting time-parallelism in case that an application is specified as a task graph following the data-flow semantics, such as a KPN (Kahn Process Network) or a data flow graph. Time-parallel simulation enables parallel execution of tasks in different intervals in the timeline by resolving data dependencies between them with redundant host code execution. The proposed technique provides higher degree of parallelism beyond the number of processors in the target architecture. Experiments with real-life multimedia examples prove the effectiveness of the proposed approach.