A level shifter circuit design by using input/output voltage monitoring technique for ultra-low voltage digital CMOS LSIs

Abstract

In this paper, we propose a level shifter circuit capable with a wide input voltage range. The circuit is based on a conventional two-stage comparator, and has a distinctive feature in current generation scheme by monitoring input and output logic levels. The proposed circuit can convert low voltage input digital signals into high voltage output digital signals. The circuit achieves low power operation because it dissipates operating current only when the input signals change. A SPICE demonstrated that the circuit can convert low voltage signals of 0.4-V into 3 V. The power dissipation was 6 nW at 0.4-V and 1-kHz input pulse. The circuit is useful for an ultra-low voltage digital circuit system co-existing with high voltage digital circuit systems.