500 nm-sized Ni-TSVwith Aspect Ratio 20 for Future 3D-LSIs_A Low-Cost Electroless-Ni Plating Approach

M. Murugesan, T. Fukushima, M. Koyanagi
{"title":"500 nm-sized Ni-TSVwith Aspect Ratio 20 for Future 3D-LSIs_A Low-Cost Electroless-Ni Plating Approach","authors":"M. Murugesan, T. Fukushima, M. Koyanagi","doi":"10.1109/ASMC.2019.8791781","DOIUrl":null,"url":null,"abstract":"A 500 nm-width nickel-through-Si-via (Ni-TSV) for future 3D-LSI/IC integration at chip-to-wafer/wafer-to-wafer level was proposed and fabricated successfully on 12-inch LSI wafer. An aspect ratio of 20 for 500 nm-width Ni-TSVs has been realized. A modified electroless-Ni plating process was employed to seamlessly and nearly completely fill these Ni-TSVs. We were able to fabricate Ni-TSVs successfully with reproducibility by using via-last approach.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"16 4","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.2019.8791781","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

Abstract

A 500 nm-width nickel-through-Si-via (Ni-TSV) for future 3D-LSI/IC integration at chip-to-wafer/wafer-to-wafer level was proposed and fabricated successfully on 12-inch LSI wafer. An aspect ratio of 20 for 500 nm-width Ni-TSVs has been realized. A modified electroless-Ni plating process was employed to seamlessly and nearly completely fill these Ni-TSVs. We were able to fabricate Ni-TSVs successfully with reproducibility by using via-last approach.
未来3D-LSIs_A低成本化学镀镍方法的宽高比为20的500纳米ni - tsv
提出了一种用于未来芯片到晶圆/晶圆级3d LSI/IC集成的500纳米宽镍通硅孔(Ni-TSV),并在12英寸LSI晶圆上成功制造。实现了500 nm宽的ni - tsv的长宽比为20。采用改进的化学镀镍工艺无缝地、几乎完全地填充了这些ni - tsv。我们成功地用过孔法制备了ni - tsv,具有可重复性。
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