Device-Level Performance Comparison of Some Pocket Engineered III-V/Si Hetero-Junction Vertical Tunnel Field Effect Transistor

Abstract

This work reports a comparative study of vertically grown III-V/Si heterojunction based n-type tunnel field effect transistor (TFET) architectures: GaSb/Si heterojunction vertical TFET with source pocket and InAs/Si heterojunction vertical TFET with source pocket. For the first time GaSb/Si heterojunction based vertical TFET is proposed here whereas InAs/Si based heterojunction TFET is well explored in literature. Low band gap semiconductor like InAs and GaSb are considered in source region of TFET to reduce the tunneling width for enhancing ON-current. Source pocket is adopted to enhance the sub-threshold performance of the devices. Performance comparison is done in terms of different dc parameters like average sub-threshold swing (SS), ION, IOFF, threshold voltage (VT) and ION/IOFF ratio of the TFETs presented for study. In addition to this, the intrinsic capacitance like CGD and temperature reliability studies are done for both the devices presented for study.