Vertical pass transistor design for sub-100 nm DRAM technologies

Abstract

The 8F/sup 2/ vertical transistor DRAM cell is a cost-efficient, litho-friendly structure suitable for scaling to sub-100 nm ground rules. In this paper, we report on device design considerations for vertical pass transistors used in ultra-dense DRAM technologies. A double-gate, vertical DRAM pass transistor that meets 1fA off-current requirement and offers twice the current drive of comparable 175 nm planar devices will be presented. Additionally, structural features unique to vertical devices are highlighted.