Graphical optimization method applied to a 6 GHz single-ended ring oscillators

Abstract

In this paper, we present a graphical optimization method in order to optimize the CMOS Ring oscillators. The design constraints equations of phase noise, tuning range, power consumption and start-up condition are presented in the same plan to find the optimal sizing of all components of CMOS ring oscillators. The optimized ring oscillator characteristics a simulated phase noise of -111.25dBc/Hz at 10 MHz offset from a 6 GHz. The VCO turns from 7.74 GHz to 4.26 GHz with a tuning voltage that varies from 0.5 V to 1.4 V, and the designed oscillator dissipates only 7 mW at 6 GHz carrier. Simulation verifies the theory approximations done by the graphical optimization method.