Design of self checking circuits based on FPGA

Abstract

The paper focuses on error detection in circuits implemented in FPGAs using error detection codes (ED codes). The incorrect function of a given combinational circuit has to be detected and signalized at the time of its appearance and before its further distribution. It means that a safe operation is guaranteed. The ability to detect an error without stopping circuit function is called concurrent error detection (CED). We have used combinational circuits only to simplify testing process. A previous research was based on benchmarks described by tables. In some cases benchmarks with many inputs cannot be described by tables easily. The benchmarks used in our experiments to compute a quality of the code are described by equations. All of them will be implemented in XILINX FPGA circuits. Therefore the fault model considers the way of configuration data storage in memory. This work is a part of a more complex methodology of fault tolerant design based on FPGAs with a possibility to reconfigure the faulty part of the circuit.