Analysis and key specifications of a novel frequency synthesizer architecture for multi-standard transceivers

Abstract

Future mobile terminals will need to support various wireless standards. Software defined radios (SDR), enabling multi-standard wireless terminals, provide the necessary flexibility for seamless wireless communications. A key challenge in such systems is to have one reconfigurable frequency synthesizer, acting as the local oscillator (LO) and covering all the frequency bands of the considered standards. In this way, silicon area, hence cost, is reduced. To address this need, a novel frequency synthesizer architecture is proposed enabling the generation of quadrature LO-signals over an extremely wide frequency range from one state-of-the-art voltage controlled oscillator (VCO) only . This paper first examines the operating principle of this novel architecture. Then, the key specifications for the individual building blocks are derived, for a representative, large set of standards. Thus specified, the frequency synthesizer covers I/Q LO generation for frequencies ranging from 174 MHz to 5.825 GHz, based on a single VCO with a center frequency of 3.9 GHz and tuning range of /spl plusmn/ 15%, and followed by programmable dividers and a reconfigurable, 8-delay cell delay locked loop (DLL). Finally, estimated power consumption numbers for 130 nm CMOS are given as examples. This novel frequency synthesizer architecture is a key enabler for a true SDR front-end.