A dual-core ASIC architecture for high-speed on-board image compression with JPEG2000

Abstract

We propose a dual core JPEG2000 architecture which aims to compress high resolution multichannel images in real time. The proposed architecture handles both lossless and Rate Distortion-Optimized lossy compression schemes of JPEG2000. The dual core JPEG2000 architecture is implemented and simulated on a Xilinx Virtex-5 Series FPGA. The simulation results show that the proposed architecture can encode up to 200Mbits at 100MHz clock speed.