Implementation and analysis of configurable Real Time Address Trace Compressor for embedded microprocessors

Abstract

Real-Time Address Trace Compression (RTATC) is a very useful method for debugging or analyzing software programs running on a processor-based system. Address trace compression means that the instruction addresses, which are produced in the instruction-fetch stage of the microprocessor, are compressed and out putted for later reconstruction and analysis. This paper presents a kind of RTATC method which includes three phases: branch filtering, address encoding and address compressing. A synthesizable RTL code for this method is constructed and integrated with a DSP&CPU processor to analyze the compressing effect and evaluate the hardware cost. The results show that our hardware is capable of real-time compression and achieving a very high compression ratio.