Pulse based Acyclic Asynchronous Pipelines for Combinational Logic Circuits

Abstract

Asynchronous circuits are a promising design style for high performance and low-power applications. Among the templates, pipeline templates are popular in high-performance systems. In asynchronous pipelines, every stage has to wait for its successive stage to complete its operation as they were interrelated to each other by hand shaking protocols. Asynchronous circuits are cyclic in nature. Current EDA tools support only acyclic circuits for timing calculations. The present tools have to adapt to new algorithms in order to support full cyclic circuits. The work in this paper proposes an asynchronous pipelining template without handshaking protocols which will be acyclic in nature so that timing calculations are possible with the current EDA tools without the need of adapting to any new algorithms.