Asynchronous Serial Infrastructure Using FPIO

Abstract

"Tour Pin Input Output" (FPIO) is a delayinsensitive asynchronous bit-serial multi-chip management protocol which surpasses "Serial Peripheral Interface" (SPI) by eliminating timing races, waiting for peripherals to acknowledge, using unidirectional fanout-1 full-swing signals, eliminating chip select wires, and scaling to rings of dozens of chips using less wiring. The message protocol over FPIO supports on-chip tree and ring topologies to connect internal interfaces such as virtualized wires, scan chains, NoC message interfaces, and circuit testers. Intel’s Loihi neuromorphic processor and related chips use this new infrastructure. We propose these protocols as an open standard for serial management, especially suited for asynchronous chips.