2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

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2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) - 最新文献

Understanding the optimization of sub-45nm FinFET devices for ESD applications

Pub Date : 2007-12-12 DOI: 10.1109/EOSESD.2007.4401780 D. Trémouilles, S. Thijs, C. Russ, J. Schneider, C. Duvvury, N. Collaert, D. Linten, M. Scholz, M. Jurczak, H. Gossner, G. Groeseneken

Modeling snapback of LVTSCR devices for ESD circuit simulation using advanced BJT and MOS models

Pub Date : 2007-12-12 DOI: 10.1109/EOSESD.2007.4401749 Y. Zhou, J. Hajjar, A. Righter, K. Lisiak

Do we expect ESD failures in an EPA designed according to international standards? The need for a process related risk analysis

Pub Date : 2007-12-12 DOI: 10.1109/EOSESD.2007.4401751 R. Gaertner

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