Discrete Cosine Transform Hardware Accelerator in Parallel Ultra-low Power System

已完结 20 由 quinn 发布于 2026/3/25 15:16:59

DOI:10.1109/ELMAR52657.2021.9550946
文献类型：期刊论文
补充材料：只需要正文
文献链接：https://doi.org/10.1109/ELMAR52657.2021.9550946

其它数据库

Abstract：In this paper, the architecture of a fully pipelined discrete cosine transform ( DCT) hardware accelerator for a JPEG encoder is proposed. The integration of the accelerator into the paralle

应助信息

求助已完结，文件已删除 如有需求请重新发布求助一键发布

感谢使用Book学术
本站所有文献仅供个人学习和参考，请勿将文件进行传播。共同遵守网站规定和相关知识产权规定。

上一个求助:其它数据库Naturally Fractured Carbonate Reservoir Characterization: A Case Study of a Mature High-Pour Point Oil Field in Hungary 下一个求助:Institute of Electrical and Electronics Engineers (IEEE)Semi-Supervised VQA Multi-Modal Explanation via Self-Critical Learning.