A 14-GS/s 8-bit time-interleaved SAR ADC with multi-path bootstrapped switch and low-jitter sampling PLL in 28-nm CMOS

已完结 20 由王泽旭发布于 2025/7/26 12:52:55

DOI:10.1016/j.mejo.2025.106770
作者：Jiawei Ding , Xuan Guo , Shan Lu , Qing Su , Tao liu , Hanbo Jia , Yihan Li , Xinyu Liu
文献类型：期刊论文
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Elsevier

Abstract：This paper presents an 8-bit, 14-GS/s, 16-channel time-interleaved successive approximation register (TI-SAR) analog-to-digital converter (ADC). A multi-path bootstrapped switch is proposed

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