Teng Wang, Lei Zhao, Ziyi Hu, Zheng Xie, Xin'an Wang
{"title":"H.264编码器色度插值器的硬件高效实现","authors":"Teng Wang, Lei Zhao, Ziyi Hu, Zheng Xie, Xin'an Wang","doi":"10.1109/EDSSC.2011.6117699","DOIUrl":null,"url":null,"abstract":"In this paper, an implementation of the chroma interpolator with great hardware reuse and no multipliers for H.264 encoders is proposed. First, the characteristic of the chroma interpolation is analyzed to obtain an optimized decomposition scheme, with which the chroma interpolation can be realized with arithmetic elements which are comprised of only adders. The design was prototyped within a Xilinx Virtex6 FPGA at 245 MHz. The design was also synthesized with SMIC 130ns CMOS technology at 200 MHz, which can support a real-time HDTV application.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"33 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A hardware efficient implementation of chroma interpolator for H.264 encoders\",\"authors\":\"Teng Wang, Lei Zhao, Ziyi Hu, Zheng Xie, Xin'an Wang\",\"doi\":\"10.1109/EDSSC.2011.6117699\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, an implementation of the chroma interpolator with great hardware reuse and no multipliers for H.264 encoders is proposed. First, the characteristic of the chroma interpolation is analyzed to obtain an optimized decomposition scheme, with which the chroma interpolation can be realized with arithmetic elements which are comprised of only adders. The design was prototyped within a Xilinx Virtex6 FPGA at 245 MHz. The design was also synthesized with SMIC 130ns CMOS technology at 200 MHz, which can support a real-time HDTV application.\",\"PeriodicalId\":6363,\"journal\":{\"name\":\"2011 IEEE International Conference of Electron Devices and Solid-State Circuits\",\"volume\":\"33 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International Conference of Electron Devices and Solid-State Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2011.6117699\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2011.6117699","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A hardware efficient implementation of chroma interpolator for H.264 encoders
In this paper, an implementation of the chroma interpolator with great hardware reuse and no multipliers for H.264 encoders is proposed. First, the characteristic of the chroma interpolation is analyzed to obtain an optimized decomposition scheme, with which the chroma interpolation can be realized with arithmetic elements which are comprised of only adders. The design was prototyped within a Xilinx Virtex6 FPGA at 245 MHz. The design was also synthesized with SMIC 130ns CMOS technology at 200 MHz, which can support a real-time HDTV application.