保持数字时钟同步

IF 0.5 Q4 COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS

Parallel Processing Letters Pub Date : 1991-09-01 DOI:10.1142/S0129626491000161

A. Arora, S. Dolev, M. Gouda

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引用次数: 102

摘要

同时触发时钟的系统被设计为稳定的:如果时钟值不同，系统保证收敛到所有时钟值相同的状态，并随后保持相同。对于N时钟系统，该设计使用N个2logN位的寄存器，并保证在N2个“触发器”内收敛到相同的值。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Maintaining Digital Clocks in Step

A system of simultaneously triggered clocks is designed to be stabilizing: if the clock values ever differ, the system is guaranteed to converge to a state where all clock values are identical, and are subsequently maintained to be identical. For an N-clock system, the design uses N registers of 2logN bits each and guarantees convergence to identical values within N2 "triggers".

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来源期刊

Parallel Processing Letters COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS-

CiteScore

0.90

自引率

25.00%

发文量

期刊介绍： Parallel Processing Letters (PPL) aims to rapidly disseminate results on a worldwide basis in the field of parallel processing in the form of short papers. It fills the need for an information vehicle which can convey recent achievements and further the exchange of scientific information in the field. This journal has a wide scope and topics covered included: - design and analysis of parallel and distributed algorithms - theory of parallel computation - parallel programming languages - parallel programming environments - parallel architectures and VLSI circuits