一种输入为0.6-1V的无电容异步数字LDO，具有快速瞬态响应，在65nm CMOS中在500mA负载范围内实现9.5b

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI:10.1109/ESSCIRC.2015.7313858

Fan Yang, P. Mok

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引用次数: 26

摘要

提出了一种具有自适应尺寸和快速瞬态响应的65nm外部无电容异步数字低差稳压器(DLDO)。在低至0.6V至1V的宽输入电压范围内工作，该DLDO能够在50mV降压下提供500mA的最大电流。所提出的以行-列-位三维功率级为特征的自适应尺寸及其异步自适应数字管道控制，能够对纳秒级负载电流变化和200mV / 10ns基准电压切换进行快速瞬态响应，并在5mV输出纹波下具有768电平(~9.5位)的精细分辨率。该DLDO在稳定工作时所消耗的静态电流在整个输入范围内低至300μA。

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A 0.6–1V input capacitor-less asynchronous digital LDO with fast transient response achieving 9.5b over 500mA loading range in 65-nm CMOS

A 65-nm external capacitor-less asynchronous digital low drop-out regulator (DLDO) with adaptive sizing and fast transient response is presented in this paper. Operating at a wide input voltage range from as low as 0.6V to 1V, this DLDO is capable of delivering a maximum current of 500mA with 50mV drop-out voltage. The proposed adaptive sizing featured by row-column-bit 3-dimensional (3D) power stage and its asynchronous adaptive digital pipeline control have enabled a fast transient response to nanoseconds' loading current change and a 200mV per 10ns reference voltage switching, as well as a fine resolution of 768 levels (~9.5 bits) with a 5mV output ripple. The quiescent current consumed by this DLDO at steady operation is as low as 300μA over the whole input range.

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ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)

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