图像压缩提升小波乘子的有符号二幂表达式

Y. Tonomura, M. Iwahashi, T. Tsubone, N. Kambayashi
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引用次数: 0

摘要

在图像压缩方面,离散余弦变换(DCT)和小波变换(DWT)等频率变换已经得到了广泛的应用。在这些转换中使用的乘数系数通常被定义为实数,但它们在硬件配置中由有限的字长近似表示。由于前向和后向变换的系数值不匹配,这将导致重构图像的退化。为了减少由于系数不匹配导致的重构图像的退化,在设置有限字长时可以提供足够长的字长。然而,由于压缩后的图像数据通常在熵编码之前进行量化处理,因此大于一定长度的字长会导致冗余。因此,本文提出了一种方法,该方法采用有符号的2次幂(SPT)表示来表示每个乘法器的系数值,使用2次幂的和,且项数尽可能少(有限),从而使系数失配引起的误差小于量化引起的误差。这样,就可以构造一个最小尺寸的小波电路,在这个小波电路中,前向变换和后向变换之间的系数不匹配的影响不能被视觉识别。用HDL语言进行的实验证实,与每个乘法器系数赋2的相同次幂和的电路相比,所提出的方法所使用的电路结构的尺寸可减少约50%。©2007 Wiley期刊公司电子工程学报,2009,31 (7):557 - 557;在线发表于Wiley InterScience (www.interscience.wiley.com)。DOI 10.1002 / ecjc.20272
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Signed Power-of-Two Expression for Multipliers of Lifting Wavelet for Image Compression
For image compression, frequency conversions such as the discrete cosine transform (DCT) and the wavelet transform (DWT) have been widely used. The multiplier coefficients used in these conversions are in general defined as real numbers, but they are approximated by a finite word length in the hardware configuration. This causes degradation of the reconstructed images due to mismatch of the coefficient values for the forward and backward transforms. In order to reduce the degradation of the reconstructed images caused by coefficient mismatch, a sufficiently long word length can be provided in setting the finite word length. However, since the compressed image data undergo quantization processing prior to entropy encoding in general, a word length greater than a certain length causes redundancy. Hence, this paper proposes a method in which the coefficient values of each multiplier are provided by the signed power-of-two (SPT) representation, using a sum of powers of 2 with as small a (finite) number of terms as possible, so that the error caused by coefficient mismatch is smaller than the error caused by quantization. In this way, a minimum-size wavelet circuit can be constructed in which the effect of coefficient mismatch between the forward and backward transformations cannot be visually recognized. It was experimentally confirmed by an experiment using the HDL language that the size of the circuit configuration used in the proposed method could be reduced by about 50% in comparison with the circuit in which the sum of the same number of powers of 2 is assigned to each multiplier coefficient. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 90(7): 47– 57, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20272
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