3.5/7.0/ 14gb /s多速率时钟和数据恢复电路,带多模旋转二进制鉴相器

Ki-Hyun Pyun, D. Kwon, W. Choi
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引用次数: 1

摘要

实现了一种新型的多速率时钟和数据恢复(CDR)电路,可以在3.5、7.0和14gb /s的多种数据速率下工作。多模式旋转二进制鉴相器支持全速率,半速率和四分之一速率CDR操作,只有一个电压控制振荡器。采用65nm CMOS技术实现的CDR原型电路成功地实现了多速率运行,能量效率为0.64pJ/bit,芯片尺寸为0.017mm2,两者都比传统的多速率CDR电路小得多。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector
A new type of multi-rate clock and data recovery (CDR) circuit is realized that can operate at multiple data rates of 3.5, 7.0 and 14-Gb/s. A multi-mode rotational binary phase detector supports full-rate, half-rate and quarter-rate CDR operation with only one voltage-controlled oscillator. A prototype CDR circuit implemented in 65nm CMOS technology successfully demonstrates the multi-rate operation with energy efficiency of 0.64pJ/bit and chip size of 0.017mm2, both of which are much less than those of conventional multi-rate CDR circuits.
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