1.6 ns访问，1ghz双向集预测和求和索引64 kbyte数据缓存

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI:10.1109/VLSIC.2000.852896

J. Silberman, N. Aoki, N. Kojima, Sang Dhong

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引用次数: 2

摘要

64-kByte缓存利用SRAM数组、翻译数组和目录中的组合地址生成和字行解码。在解码路径中，双向关联缓存中的集合选择通过访问内置到解码器中的和索引数组中的存储预测来代替后期选择。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 1.6 ns access, 1 GHz two-way set-predicted and sum-indexed 64-kByte data cache

A 64-kByte cache exploits combined address generation and word line decoding in the SRAM array, translation array, and directory. In place of a late select, set selection in the two-way associative cache is accomplished in the decode path by accessing a stored prediction from a sum-indexed array built into the decoder.

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来源期刊

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

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