{"title":"一种新的高速低功耗soc多晶体管参数设计方法","authors":"K. Takeuchi, T. Mogami","doi":"10.1109/IEDM.2001.979558","DOIUrl":null,"url":null,"abstract":"A simple method for determining the optimal use of multiple transistor parameters (MP), i.e. multiple V/sub TH/, V/sub DD/, and T/sub OX/, for System-on-a-Chip's (SoC's) is proposed. Reasonable optimization results are automatically obtained for various SoC configurations, which is difficult to achieve intuitively. It was found that the MP design is particularly effective for SoC's consisting of circuit blocks with different speed requirements.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"89 1","pages":"22.6.1-22.6.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A new multiple transistor parameter design methodology for high speed low power SoCs\",\"authors\":\"K. Takeuchi, T. Mogami\",\"doi\":\"10.1109/IEDM.2001.979558\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A simple method for determining the optimal use of multiple transistor parameters (MP), i.e. multiple V/sub TH/, V/sub DD/, and T/sub OX/, for System-on-a-Chip's (SoC's) is proposed. Reasonable optimization results are automatically obtained for various SoC configurations, which is difficult to achieve intuitively. It was found that the MP design is particularly effective for SoC's consisting of circuit blocks with different speed requirements.\",\"PeriodicalId\":13825,\"journal\":{\"name\":\"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)\",\"volume\":\"89 1\",\"pages\":\"22.6.1-22.6.4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-12-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2001.979558\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2001.979558","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new multiple transistor parameter design methodology for high speed low power SoCs
A simple method for determining the optimal use of multiple transistor parameters (MP), i.e. multiple V/sub TH/, V/sub DD/, and T/sub OX/, for System-on-a-Chip's (SoC's) is proposed. Reasonable optimization results are automatically obtained for various SoC configurations, which is difficult to achieve intuitively. It was found that the MP design is particularly effective for SoC's consisting of circuit blocks with different speed requirements.
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