基于4阶100μA二极管c的滤波器，5dBm-IIP3，截止频率为24MHz

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI:10.1109/ESSCIRC.2015.7313822

Antonio A. D'Amico, M. Matteis, S. D’Amico, C. D. Berti, L. Crespi, A. Baschirotto

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引用次数: 1

摘要

本文提出了一种带宽为24MHz的四阶低通连续时间滤波器。该结构采用交叉耦合MOS晶体管，结合电容和电阻，合成了两个复杂共轭极对。该滤波器经过设计和优化，具有沿所有滤波器通带的高线性度，特别是在截止频率边缘。该滤波器在1.8V电压下功耗为100μA，极功耗为45μW，输入参考噪声为150μVRMS，在2-3MHz输入音调时IIP3为16dBm，在截止频率附近IIP3为5dBm。

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A 4th-order 100μA diode-C-based filter with 5dBm-IIP3 at the 24MHz cut-off frequency

This paper presents a 4th-order low-pass continuous-time filter with 24MHz bandwidth. Using cross-coupled MOS transistors combined with capacitors and resistors, this architecture synthesizes two complex-conjugate-poles pairs. The filter is designed and optimized to feature high-linearity along all filter passband, and, in particular, at the cut-off frequency edge. The filter consumes 100μA with 1.8V voltage supply, and achieves 45μW/pole power consumption, 150μVRMS input-referred noise, 16dBm IIP3 with 2-3MHz input tones and 5dBm IIP3 near the cut frequency.

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ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)

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