基于Vedic数学和Booth-Wallace树乘法器的高效nxn乘法器的实现

2019 International Conference on Power Electronics, Control and Automation (ICPECA) Pub Date : 2019-11-01 DOI:10.1109/ICPECA47973.2019.8975673

A. Jain, Somya Bansal, Shaheen Khan, S. Akhter, Saurabh Chaturvedi

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引用次数: 7

摘要

本文提出了一种基于吠陀数学和布斯-华莱士树乘法器相结合的新型乘法器算法的HDL实现。一个$8 \乘以8$乘法器在VHDL中实现。HDL代码分别使用ModelSim和Xilinx ISE 14.1进行模拟和合成。本文比较了不同算法实现的8位乘法器的性能参数。对比结果表明，该算法比其他乘法器算法速度更快。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Implementation of an Efficient N× N Multiplier Based on Vedic Mathematics and Booth-Wallace Tree Multiplier

The paper presents the HDL implementation of a novel multiplier algorithm based on the combination of Vedic mathematics and Booth-Wallace tree multiplier. An $8 \times 8$ multiplier is implemented in VHDL. The HDL code is simulated and synthesized using ModelSim and Xilinx ISE 14.1, respectively. The performance parameters of 8-bit multipliers implemented using various algorithms are compared in this paper. The comparison results exhibit that the proposed algorithm is faster than other multiplier algorithms.

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来源期刊

2019 International Conference on Power Electronics, Control and Automation (ICPECA)

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