低功耗多核SoC，两个32核集群通过基于树的NoC连接，用于多媒体应用

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243834

Hui Xu, J. Tanabe, Hiroyuki Usui, Soichiro Hosoda, T. Sano, Kazumasa Yamamoto, T. Kodaka, N. Nonogaki, Nau Ozaki, T. Miyamori

{"title":"低功耗多核SoC，两个32核集群通过基于树的NoC连接，用于多媒体应用","authors":"Hui Xu, J. Tanabe, Hiroyuki Usui, Soichiro Hosoda, T. Sano, Kazumasa Yamamoto, T. Kodaka, N. Nonogaki, Nau Ozaki, T. Miyamori","doi":"10.1109/VLSIC.2012.6243834","DOIUrl":null,"url":null,"abstract":"A low-power many-core SoC for multimedia applications is implemented in 40nm CMOS technology. Within a 210mm2 die, two 32-core clusters are integrated with dynamically reconfigurable processors, hardware accelerators, 2-channel DDR3 I/Fs, and other peripherals. Processor cores in the cluster share a 2MB L2 cache connected through a tree-based Network-on-Chip (NoC). The high scalability and low power consumption are accomplished by parallelized firmware for multimedia applications, such as the H.264 1080p 30fps decoding under 500mW and the super resolution 4K2K 15fps image processing under 800mW.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"35 1","pages":"150-151"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications\",\"authors\":\"Hui Xu, J. Tanabe, Hiroyuki Usui, Soichiro Hosoda, T. Sano, Kazumasa Yamamoto, T. Kodaka, N. Nonogaki, Nau Ozaki, T. Miyamori\",\"doi\":\"10.1109/VLSIC.2012.6243834\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low-power many-core SoC for multimedia applications is implemented in 40nm CMOS technology. Within a 210mm2 die, two 32-core clusters are integrated with dynamically reconfigurable processors, hardware accelerators, 2-channel DDR3 I/Fs, and other peripherals. Processor cores in the cluster share a 2MB L2 cache connected through a tree-based Network-on-Chip (NoC). The high scalability and low power consumption are accomplished by parallelized firmware for multimedia applications, such as the H.264 1080p 30fps decoding under 500mW and the super resolution 4K2K 15fps image processing under 800mW.\",\"PeriodicalId\":6347,\"journal\":{\"name\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"volume\":\"35 1\",\"pages\":\"150-151\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2012.6243834\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Circuits (VLSIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2012.6243834","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 19

摘要

采用40nm CMOS技术实现了一款适用于多媒体应用的低功耗多核SoC。在一个210mm2的芯片中，两个32核集群集成了动态可重构处理器、硬件加速器、2通道DDR3 I/ f和其他外设。集群中的处理器内核共享通过基于树的片上网络(NoC)连接的2MB L2缓存。多媒体应用的并行固件实现了高可扩展性和低功耗，例如在500mW下的H.264 1080p 30fps解码和800mW下的超分辨率4K2K 15fps图像处理。

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A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications

A low-power many-core SoC for multimedia applications is implemented in 40nm CMOS technology. Within a 210mm2 die, two 32-core clusters are integrated with dynamically reconfigurable processors, hardware accelerators, 2-channel DDR3 I/Fs, and other peripherals. Processor cores in the cluster share a 2MB L2 cache connected through a tree-based Network-on-Chip (NoC). The high scalability and low power consumption are accomplished by parallelized firmware for multimedia applications, such as the H.264 1080p 30fps decoding under 500mW and the super resolution 4K2K 15fps image processing under 800mW.

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2012 Symposium on VLSI Circuits (VLSIC)

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