一种采用标准CMOS工艺的新型相位逆变器的d波段紧凑型大鼠赛跑耦合器

Debin Hou, W. Hong, W. Goh, A. Arasu, Y. Xiong, Chang Liu, M. Madihian
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引用次数: 8

摘要

本文介绍了一种采用新型相位逆变器的d波段片上大鼠竞赛耦合器,并采用标准的CMOS工艺进行了研制。基于特性阻抗和相位差分析的结构简单的逆变器在宽频带和紧凑的毫米波频率范围内的应用已经显示出它的潜力。与传统结构相比,使用所提出的相位逆变器开发的老鼠竞赛耦合器的尺寸减小了40%,带宽提高了60%以上。在整个d波段范围内,耦合器的测量幅度和相位不平衡分别在0.5 dB和15°以内。端口到端口的隔离度在d频段范围内优于25 dB,在118 GHz时最高为41 dB。插入损耗达到1.2±0.3 dB,耦合器的珊瑚尺寸仅为290 × 162µm2。提出的耦合器在100 GHz以上的单芯片系统中具有巨大的集成潜力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A D-band compact rat-race coupler using novel phase inverter in standard CMOS process
This paper describes a D-band on-chip rat-race coupler using a novel phase inverter and developed in a standard CMOS process. The simple structural phase inverter which is based on the characteristic impedance and phase difference analysis has demonstrated its potential for wideband and compact millimeter-wave frequency range applications. The developed rat-race coupler using the proposed phase inverter, features a 40% size reduction and over 60% bandwidth improvement compared to conventional structures. In the complete D-band range, measured amplitude and phase imbalances for the coupler are within 0.5 dB and 15°, respectively. The port-to-port isolation is better than 25 dB in the D-band range with the highest value of 41 dB at 118 GHz. The insertion loss achieves 1.2 ± 0.3 dB and the coral size of the coupler is only 290 × 162 µm2. The proposed coupler has a huge potential for integration in single-chip systems over 100 GHz.
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