一个0.44fJ/转换步长11b 600KS/s带半静止DAC的SAR ADC

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573519

Sung-En Hsieh, C. Hsieh

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引用次数: 23

摘要

一个0.3V 600KS/s 11b SAR ADC，具有半静息(SR) DAC、级联输入(CI)比较器和双轨到轨输入范围。SR DAC消耗的开关能量仅为最先进器件的6-13.5%。CI比较器仅消耗49%的功率和66%的决策时间，并具有×3前置增益提升。该样机的SNDR为58.7dB, ENOB为9.46b，功率为187nW, FoM为0.44fJ/ vs .-step。

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A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC

A 0.3V 600KS/s 11b SAR ADC with semi-resting (SR) DAC, cascade-input (CI) comparator, and double rail-to-rail input range is implemented in 90nm CMOS. The SR DAC consumes only 6-13.5% switching energy of the state-of-the-art works. The CI comparator consumes only 49% of power and 66% of decision time with an ×3 front-stage gain boost. The prototype achieves a SNDR of 58.7dB, an ENOB of 9.46b, a power of 187nW, and a resulting FoM of 0.44fJ/conv.-step.

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2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

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