自适应带宽dll和pll使用稳压供应CMOS缓冲器

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI:10.1109/VLSIC.2000.852868

S. Sidiropoulos, Dean Liu, Jaeha Kim, Gu-Yeon Wei, Mark Horowitz

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引用次数: 146

摘要

提出了一种利用CMOS稳压电源缓冲器设计dll和pll的技术。通过调整电荷泵电流和调节放大器的输出电阻，所提出的环路实现了跟踪工作频率的宽带宽、恒定的阻尼因子、大的工作范围和低噪声灵敏度。在0.35-/spl mu/m CMOS工艺中设计的原型回路具有>10倍的工作范围和小于1%的输入跟踪抖动。

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Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers

A technique for designing DLLs and PLLs using CMOS buffers with a regulated supply is presented. By scaling the charge pump current and the output resistance of the regulating amplifier, the proposed loops achieve a wide bandwidth that tracks the operating frequency, a constant damping factor, large operating range and low noise sensitivity. Prototype loops designed in 0.35-/spl mu/m CMOS processes exhibit >10x operating range and less than 1% input tracking jitter.

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来源期刊

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

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