基于OpenSPRAC架构的高速缓存交叉栏设计

2008 International Conference on Electronic Packaging Technology & High Density Packaging Pub Date : 2008-07-28 DOI:10.1109/ICEPT.2008.4606979

Xi-chuan Wang, Bin-feng Qian

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引用次数: 2

摘要

多核处理器在服务器和台式计算机上得到了广泛的应用。本文介绍了用于SPARC T2多核处理器的高速缓存横杆的结构。核心可以使用缓存交叉条来交换L2缓存银行中的数据。多核之间可以通过共享二级缓存库中的数据进行通信。通过对CCX的分析，提出了一种连接多核和缓存库的协议。高速缓存交叉条是在SMIC 0.13芯片上实现的，并带有设计编译器，可以运行在200mhz频率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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The design of the cache crossbar based on OpenSPRAC architecture

Multi-core processor is widely used on the server and desktop computer nowadays. This paper describes the structure of a cache crossbar which used in the multi-core processor SPARC T2. The cores can use the cache crossbar to exchange the data in the L2 cache banks. The multi cores can communicate among each other core by sharing the data in the L2 cache banks. And with the analysis of the CCX, this paper provides a protocol for connecting multi cores and cache banks. The cache crossbar is implemented in SMIC 0.13 mum with design compiler and can run at 200 MHz.

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2008 International Conference on Electronic Packaging Technology & High Density Packaging

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