A data-driven processor for alleviating bottlenecks of sequential programs and maintaining multiprocessing capability

Existing data-driven processors offer the advantages of being able to naturally resolve the problems inherent in a wide variety of granularities of parallelism, and of being able to multiprocess without overhead. However, because an instruction is not issued until the instruction that generates the source operand finishes executing, a delay equal to the number of stages in the pipeline occurs before an instruction that has a data-dependency relationship can be executed. As a result, portions of sequential processing in a program become a bottleneck. The authors are therefore in the process of developing an LSI processor that is able to retain the advantages of conventional data-driven processors while being able to efficiently execute blocks of sequential processing. This paper presents and evaluates the performance of the proposed execution model and pipeline structure of this processor. This processor uses the same pipeline to perform instruction level multiprocessing of data-driven programs that issue instructions based on the data-dependency relationships and control-driven programs that issue instructions sequentially based on a program counter. The effectiveness of parallel processing by data-driven programs, improvements in the efficiency of sequential processing by introducing control-driven programs, and the ability to evenly share the pipeline when data-driven and control-driven programs are multiprocessing are evaluated. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 90(12): 36–49, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20358