一种RISC-V核心钢- asic的合成

Q4 Engineering

Journal of Integrated Circuits and Systems Pub Date : 2022-09-17 DOI:10.29292/jics.v17i2.548

Rafael Da Silva, Vinicius dos Santos, F´abio Petkowicz, Rafael Calc¸ada, R. Reis

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引用次数: 0

摘要

介绍了UFRGS开发的RISC-V微处理器STEEL的ASIC版本的设计流程。名为STEEL的微处理器核心实现了RISC-V规格的RV32I和Zicsr指令集。整个过程需要逻辑和物理合成，使用X-Fab 180纳米，它依赖于Cadence EDA框架。ASIC电路以19.61 MHz的最大频率工作，从物理合成中获得的估计表明功耗为10.09 mW。

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Synthesis of Steel-ASIC, a RISC-V Core

It is presented the design flow of an ASIC version of STEEL, a RISC-V microprocessor developed at UFRGS. The microprocessor core called STEEL implements the RV32I and Zicsr instruction sets of the RISC-V specifications. The whole process entails logical and physical synthesis, using the X-Fab 180 nm, which relies on the Cadence EDA framework. The ASIC circuit operates with a maximum frequency of 19.61 MHz and the estimates obtained from the physical synthesis indicates a power consumption of 10.09 mW.

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来源期刊

Journal of Integrated Circuits and Systems Engineering-Electrical and Electronic Engineering

CiteScore

0.90

自引率

0.00%

发文量

期刊介绍： This journal will present state-of-art papers on Integrated Circuits and Systems. It is an effort of both Brazilian Microelectronics Society - SBMicro and Brazilian Computer Society - SBC to create a new scientific journal covering Process and Materials, Device and Characterization, Design, Test and CAD of Integrated Circuits and Systems. The Journal of Integrated Circuits and Systems is published through Special Issues on subjects to be defined by the Editorial Board. Special issues will publish selected papers from both Brazilian Societies annual conferences, SBCCI - Symposium on Integrated Circuits and Systems and SBMicro - Symposium on Microelectronics Technology and Devices.