ADRC-based symmetric phase-locked loop structure for improving low-frequency stability of grid-connected inverters

With a small short-circuit ratio (SCR), the grid-connected inverter is prone to low-frequency oscillation instability due to the dynamic interaction between the phase-locked loop (PLL) and the weak grid. To this end, an active-disturbance-rejection-controller-based symmetric PLL (ADRC-based SyPLL) is proposed in this article to simplify the system modelling and improve the low-frequency stability of the inverter system. Specifically, the ADRC technique is applied to phase-regulated feedback control of a PLL, where an extended state observer (ESO) is used to estimate the lumped disturbance of the controlled system. A control loop symmetric to the q-axis is further designed on the d-axis of the PLL, and the d-axis information is then added at the reference generation side to eliminate the coupled frequency term in the small-signal model. A simple and accurate single-input single-output (SISO) model is thus obtained. The impedance stability analysis for grid-connected inverters shows that the proposed ADRC-based SyPLL can significantly improve the low-frequency stability margin of the system compared with the conventional PI-regulated PLL. Finally, the experimental results validate the effectiveness and superiority of the proposed method.