J. Franco, H. Arimura, S. Brus, E. Dentoni Litta, K. Croes, N. Horiguchi, B. Kaczer
{"title":"工作函数金属堆叠对多 Vth RMG CMOS 技术性能和可靠性的影响","authors":"J. Franco, H. Arimura, S. Brus, E. Dentoni Litta, K. Croes, N. Horiguchi, B. Kaczer","doi":"10.1016/j.sse.2024.108929","DOIUrl":null,"url":null,"abstract":"<div><p>Multi-<em>V<sub>th</sub></em> CMOS device technologies have become standard for System-on-Chip designs. In Replacement Gate technologies, distinct device <em>V<sub>th</sub></em>’s are achieved by deploying different work function metal stacks, and thus concerns exist about the possible chemical interaction of different gate metals with the underlying dielectrics potentially affecting the device performance and reliability. We present a comprehensive study, comprising both electrical measurements and simulations, carried out on a planar transistor platform with state-of-the-art gate stacks. Two different metal stacks are deployed to fabricate low-<em>V<sub>th</sub></em> and ultra-high <em>V<sub>th</sub></em> pMOS and nMOS device flavors. The study provides fundamental insights on the impact of TiAl-based gate metal on EOT, gate leakage, interface quality, carrier mobility, short channel performance, PBTI and NBTI reliability.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"216 ","pages":"Article 108929"},"PeriodicalIF":1.4000,"publicationDate":"2024-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Impact of work function metal stacks on the performance and reliability of multi-Vth RMG CMOS technology\",\"authors\":\"J. Franco, H. Arimura, S. Brus, E. Dentoni Litta, K. Croes, N. Horiguchi, B. Kaczer\",\"doi\":\"10.1016/j.sse.2024.108929\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>Multi-<em>V<sub>th</sub></em> CMOS device technologies have become standard for System-on-Chip designs. In Replacement Gate technologies, distinct device <em>V<sub>th</sub></em>’s are achieved by deploying different work function metal stacks, and thus concerns exist about the possible chemical interaction of different gate metals with the underlying dielectrics potentially affecting the device performance and reliability. We present a comprehensive study, comprising both electrical measurements and simulations, carried out on a planar transistor platform with state-of-the-art gate stacks. Two different metal stacks are deployed to fabricate low-<em>V<sub>th</sub></em> and ultra-high <em>V<sub>th</sub></em> pMOS and nMOS device flavors. The study provides fundamental insights on the impact of TiAl-based gate metal on EOT, gate leakage, interface quality, carrier mobility, short channel performance, PBTI and NBTI reliability.</p></div>\",\"PeriodicalId\":21909,\"journal\":{\"name\":\"Solid-state Electronics\",\"volume\":\"216 \",\"pages\":\"Article 108929\"},\"PeriodicalIF\":1.4000,\"publicationDate\":\"2024-03-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Solid-state Electronics\",\"FirstCategoryId\":\"101\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0038110124000789\",\"RegionNum\":4,\"RegionCategory\":\"物理与天体物理\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0038110124000789","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Impact of work function metal stacks on the performance and reliability of multi-Vth RMG CMOS technology
Multi-Vth CMOS device technologies have become standard for System-on-Chip designs. In Replacement Gate technologies, distinct device Vth’s are achieved by deploying different work function metal stacks, and thus concerns exist about the possible chemical interaction of different gate metals with the underlying dielectrics potentially affecting the device performance and reliability. We present a comprehensive study, comprising both electrical measurements and simulations, carried out on a planar transistor platform with state-of-the-art gate stacks. Two different metal stacks are deployed to fabricate low-Vth and ultra-high Vth pMOS and nMOS device flavors. The study provides fundamental insights on the impact of TiAl-based gate metal on EOT, gate leakage, interface quality, carrier mobility, short channel performance, PBTI and NBTI reliability.
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It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.
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