物联网设备相位频率检测器模块的优化和性能计算

Q2 Computer Science
Md. Shahriar Khan Hemel, M. Reaz, S. Ali, Mohammad Arif Sobhan Bhuiyan, Mahdi H. Miraz
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引用次数: 0

摘要

物联网(IoT)在改变我们的生活方式以及与周围环境的互动方面起着举足轻重的作用。为了应对技术的进步,必须以最快的速度获得精确度。相位频率检测器(PFD)是在物联网设备中调节和提供精确频率的关键设备。设计相位频率检测器在实现精确的相位检测、最小化死区、优化功耗以及确保各种工作频率下的稳健性能等方面都面临挑战,因此需要复杂的工程设计和创新的解决方案。本研究深入探讨了如何优化使用 90 纳米标准 CMOS 技术设计的 PFD 电路,以实现卓越的工作频率。使用 cadence virtuoso 制作和分析了高效高频 PFD 设计。研究重点是调查优化 PFD 设计的影响。经过优化的 PFD 实现了 5 GHz 的工作频率,功耗仅为 29 µW。PFD 的死区仅为 25 ps。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Optimisation and Performance Computation of a Phase Frequency Detector Module for IoT Devices
The Internet of Things (IoT) is pivotal in transforming the way we live and interact with our surroundings. To cope with the advancement in technologies, it is vital to acquire accuracy with the speed. A phase frequency detector (PFD) is a critical device to regulate and provide accurate frequency in IoT devices. Designing a PFD poses challenges in achieving precise phase detection, minimising dead zones, optimising power consumption, and ensuring robust performance across various operational frequencies, necessitating complex engineering and innovative solutions. This study delves into optimising a PFD circuit, designed using 90 nm standard CMOS technology, aiming to achieve superior operational frequencies. An efficient and high-frequency PFD design is crafted and analysed using cadence virtuoso. The study focused on investigating the impact of optimising PFD design. With the optimised PFD, an operational frequency of 5 GHz has been achieved, along with a power consumption of only 29 µW. The dead zone of the PFD was only 25 ps.
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来源期刊
Annals of Emerging Technologies in Computing
Annals of Emerging Technologies in Computing Computer Science-Computer Science (all)
CiteScore
3.50
自引率
0.00%
发文量
26
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