Sukho Lee, Seongmo Park, Jinho Han, N. Eum, Jongwon Park
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A 40MHZ dedicated hardware H.264/AVC video encoder with the reducing memory access scheme
In this paper, we present the dedicated hardware H.264/AVC video encoder with reducing memory access scheme. This engine performs 30 frame/sec with D1(720x480) resolution at 40 MHz. It has dedicated hardware architecture, memory reducing scheme, double buffering structure to decrease memory bus bandwidth and early decision mode for fast estimation at motion estimation. It supports to H.264/AVC base profile level 3. Its gate count is 427K and can be applied various application, such as, IPTV, surveillance system and portable multimedia devices to need low frequency and low power.
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