A systolic architecture for sorting an arbitrary number of elements

We propose a simple systolic VLSI sorting architecture whose main feature is the pipelined use of a sorting network of fixed I/O size p to sort an arbitrarily large data set of N elements. Our architecture is feasible for VLSI implementation and its time performance is virtually independent of the cost and depth of the underlying sorting network. Specifically, we show that by using our design N elements can be sorted in /spl Theta/(N/p log N/p) time without memory access conflicts. We also show how to use an AT/sup 2/-optimal sorting network of fixed I/O size p to construct a similar systolic architecture that sorts N elements in /spl Theta/(N/p log N/plogp) time.