采用梯度掺杂通道改善可靠性的纳米SiGe DG MOSFET数值研究

T. Bentrcia, F. Djeffal, D. Arar, M. Meguellati
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引用次数: 3

摘要

使用低带隙材料如SiGe用于DG MOSFET通道是至关重要的,因为它们与纯硅器件开发的工艺兼容。此外,SiGe材料中电子迁移率的增加对漏极电流和跨导都有积极的影响。然而,由于锗摩尔分数增加导致的带隙缩小是导致电性能下降的关键障碍。因此,我们提出了一种新的基于梯度掺杂通道的方法来提高器件的可靠性。基于Atlas二维模拟的纳米级SiGe双栅极MOSFET,包括漏极附近的界面缺陷,我们建立了数值模型来解释几种掺杂方式对纳米级晶体管抗扰性能对界面陷阱密度的影响。在这种情况下,研究了所提出设计的亚阈值特性(阈值电压、摆幅因子和栅极电流),并根据传统的均匀掺杂谱DG MOSFET特性进行了评估。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Numerical investigation of nanoscale SiGe DG MOSFET with graded doping channel for improving reliability behavior
The use of lower band gap materials such as SiGe for the DG MOSFET channel is of paramount importance given their compatibility with the process developed for pure Silicon devices. Furthermore, the increased electrons mobility in SiGe material has a positive effect on both drain current and transconductance. However, band gap narrowing due to Ge mole fraction increasing channel is a crucial obstacle that leads to electrical performance degradation. Thus, we present in this paper a novel graded doping channel-based approach to enhance the device reliability. Based on Atlas 2-D simulation of the nanoscale SiGe Double Gate MOSFET including the interface defects near the drain side, we develop numerical models to explain the impact of several doping profile on the immunity performance of the nanoscale transistor against the interface traps density. In this context, subthreshold characteristics of the proposed design (threshold voltage, swing factor and gate current) are investigated and evaluated with respect to the conventional uniform doping profile DG MOSFET characteristics.
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