一种低差线性稳压器的设计

2020 IEEE International Conference on Artificial Intelligence and Information Systems (ICAIIS) Pub Date : 2020-03-01 DOI:10.1109/ICAIIS49377.2020.9194883

Enyu Xu, X. He

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引用次数: 1

摘要

本文介绍了一种工作电压为2.5V的低压差线性稳压器。在误差放大器中加入抗超调电路，并根据电路稳定性对稳压模块进行优化;在反馈电阻网络中增加微调功能，使LDO可以根据各种需要输出1.1V、1.8V、2.2V等不同电压值。基于HLMC 40nm CMOS工艺，用Cadence软件对该电路进行了仿真。结果表明，LDO的最小抑制比为- 35dB，最大抑制比为- 56dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design of a Low-Dropout Linear Regulator

This paper introduces a low-dropout linear regulator with an operating voltage of 2.5V. An anti-overshoot circuit is added to the error amplifier, and the regulator module is optimized based on circuit stability performance; Add trim function to feedback resistance network so that LDO can output different voltage values such as 1.1V, 1.8V and 2.2V according to various needs. The circuit is simulated by Cadence based on HLMC 40nm CMOS process. The results show that the LDO has a minimum rejection ratio of −35dB and a maximum of −56dB.

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2020 IEEE International Conference on Artificial Intelligence and Information Systems (ICAIIS)

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